This invention relates generally to methods and circuit configurations for testing integrated circuits, and in particular to methods and circuit configurations for testing the efficacy of memory cells and routing resources in programmable logic devices.
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit (IC) that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. As with other types of ICs. PLDs are tested using some form of automatic test equipment (generally a xe2x80x9ctesterxe2x80x9d). One type of PLD, the field-programmable gate array (FPGA), typically includes an array (rows and columns) of configurable logic blocks (CLBs) that are programmably interconnected to each other and to programmable input/output blocks (IOBs). The CLBs include memory arrays that can be configured either as look-up tables (LUTS) that perform specific logic functions or as random-access memory (RAM). Configuration data loaded into internal configuration memory cells on the FPGA define the operation of the FPGA by determining how the CLBs, interconnections, and IOBs are configured.
Circuit vendors must verify the speed performance and functionality of each device. Testing circuits for speed performance is difficult, as many signal paths within a given IC cannot be measured directly, leading to some speculation as to their true timing characteristics. This is particularly true of FPGAs, which use embedded memory for both logic and memory functions. Furthermore, testers have tolerances that can have a significant impact on some measurements, particularly when the signal propagation time of interest is short. For example, if the tester is accurate to one nanosecond and the propagation delay of interest is measured to be one nanosecond, the actual propagation delay might be any length of time between zero and two nanoseconds. Thus, IC manufacturers tend to add relatively large margins of error, or xe2x80x9cguard bands,xe2x80x9d to ensure that their circuits will perform as advertised. Unfortunately, this practice means that those manufacturers are not able to guarantee their full speed performance, which can cost them customers in an industry where speed performance is paramount. There is therefore a need for a means of accurately characterizing the speed performance of programmable logic devices in general, and FPGAs in particular.
Functional testing of FPGAs includes exercising on-chip memory arrays to verify their data storage and retrieval capabilities. Memory testing requires more than simply writing and reading each memory location: various data patterns must be employed to ensure that each memory location is thoroughly tested. Executing such test patterns is time consuming and requires expensive test equipment, or xe2x80x9ctesters.xe2x80x9d It is therefore desirable to reduce or eliminate both the time required to test circuits and the need to employ expensive testers.
Field testing PLDs poses unique problems. A PLD programmed to perform some operation may malfunction like any IC. Unlike hard-wired ICs, however, a working PLD may include a defective resource that is not used to implement the current circuit configuration. The device may therefore work correctly until reconfigured to include some new circuitry that relies upon the defective resource. To make matters worse, different circuit configurations on a given device often have different critical paths, and may therefore exhibit different maximum clock speeds. PLDs should therefore be thoroughly tested before being reconfigured with a new design. Such testing is best performed without removing the PLD from the user""s system, and preferably without the need for expensive and cumbersome test equipment. There is therefore a need for an inexpensive and effective means of field testing PLDs.
The present invention satisfies the need for a means of effectively testing embedded memory cells and other IC resources, and further satisfies the need for an effective means of field testing programmable logic devices (PLDs). The present invention employs a test circuit that can be instantiated on a PLD to perform at-speed functional tests of PLD resources, including internal memory and routing resources. The resources to be tested are configured to create a counter circuit connected to the address terminals of a linear-feedback shift register (LFSR).
LFSRs are cyclic, in the sense that when clocked repeatedly they go through a fixed sequence of states. Consequently, an LFSR that starts with a known set of data contains a predictable set of data after a given number of clock periods. The fixed states of an LFSR are pseudo-random, with repetition rates that can be of virtually any length. The pseudo-random nature of LFSRS ensures that the internal memory and routing resources used to instantiate them are treated to a large number of permutations, provided that each LFSR is allowed to shift for a significant number of clock periods.
In accordance with the invention, an LFSR is preset to a known count (e.g., zero) and clocked a known number of times. The resulting count is then compared with a reference number. If the resulting count matches the reference number, then all of the resources used to implement the test circuit, including the memory and routing resources used to implement the LFSR, are deemed fully functional at the selected clock speed. If, however, the LFSR count does not match the reference number, then the test fails. The test can be run at a number of different speeds to determine the maximum clock speed for the device under test.
In accordance with one embodiment of the invention, a test circuit employing at least one LFSR is duplicated many times to consume as many programmable-logic resources as possible. The various test circuits are then run at a given clock speed to determine whether the tested resources function at that speed.
This summary does not purport to define the invention. The invention is defined by the claims.